The MPU 6916 is an object code-compatible extension of the Motorola M6811 microprocessor architecture (see Fig.1 below), released under the GNU General Public License (GPL-v2) as a synthesis-compliant VHDL model. The MPU 6916 internal architecture has been specially optimized for FPGA implementation and embedded systems designs, and thus does not retain hardware-level and timing compatibiliy with neither M6811 nor M6800.

Fig.1: MPU 6916 compatibility diagram

The following sections in this document present incremental overviews of the original Motorola M6800, the enhanced M6811, and the MPU 6916 architectures.

M6800 Introductory Overview

The M6800 is a minimal, first generation 8-bit microprocessor core. Despite being an obsolete architecture by itself, the M6800 has served as the foundation for the highly popular M6811, M6812, and M6816 microcontrollers.

Fig.2 shows the M6800 programming model.

Fig.2: The M6800 programming model

The M6800 features a memory-to-register intruction set, with the A and B registers acting as gneral purpose 8-bit accumulators, the X register being a 16-bit index register used to form the indexed addressing mode (in conjunction with an 8-bit signed offset), the S register being the 16-bit hardware stack pointer, the PC register acting as the 16-bit program conter, and the 8-bit CCR being the CPU's condition codes register.
As a general rule (with few exceptions), the two-operand 8-bit instructions operate on any of the two accumulators (A and B) and take the second operand from memory using any of the addressing modes, while the single-operand 8-bit instructions operate on any of the two accumulators (A and B) or directly on a memory location using any of the addressing modes.
Several arithmetic instructions can operate directly on the 16-bit "double accumulator" D formed by concatenating the contents of the A and B accumulators, with A being the high 8 bits and B being the low 8 bits of D. Although the choice of instructions operating on the D double accumulator is limited, it introduces the concept of 16-bit accumulator to an 8-bit microprocessor architecture.
The index register operations are relatively unregular, but they do provide the essential register manipulation functions.
» See the MPU 6916 Software Reference Guide for M6800 compatibility details

M6811 Introductory Overview

The M6811 architecture represents an object code-compatible extension of the original M6800 design, with the following main enhancements:

• a new index register Y has been added next to the original 6800 index register X, and all instructions that supported the X index register and/or addressing mode now also support the Y register
• several new instructions have been implemented, with the most notable addition of a 16-bit compare operation using the 16-bit D accumulator. This, together with the original M6800 16-bit additions and subtractions, provides an almost complete set of 16-bit arithmetic functions operating on the 16-bit D accumulator.

Fig.3 shows the M6811 programming model.

Fig.3: The M6811 programming model

The M6811 is supported by a complete GNU 6811 toolchain (see Fig.1), thus being compatible with a wealth of GNU-based development tools and software applications.
» See the MPU 6916 Software Reference Guide for M6811 compatibility details

MPU 6916 Introductory Overview

The MPU 6916 architecture departs from the Motorola M6812/M6816 extension strategy, and is thus not compatible with any of the M6812/M6816-specific software (including the GNU 6812 toolchains). However, unlike the M6812 and M6816, the MPU 6916 retains object code compatibility with the M6811 and M6800 architectures (see Fig.1), and thus can be used to run the unmodified GNU 6811 toolchain binaries.

The MPU 6916 upgrade path was decided based on the following key objectives:

• binary software compatibility had to be maintained with the M6811 architecture, thus allowing M6811 applications (including the complete GNU 6811 toolchain) to be used on the MPU 6916 without any changes
• the hardware overhead incurred by the MPU 6916 architectural extensions should be minimal
• the internal processor architecture should provide some form of hardware support for relocatable code and multi-threaded applications
• integrated floating point capability should be included as an optional feature
• the MPU 6916 instruction set's orthogonality should not be impaired by the new architectural extensions
• the software effort for upgrading GNU's GCC 6811 compiler to a GCC 6916 version should be minimal
• applications compiled with the GCC 6916 should offer an immediate performance boost when compared to a GCC 6811 compilation

As a first remark, an important characteristic of the GNU 6811 implementation is that its GCC compiler foundation uses three virtual index register X, Y, and Z, that are eventually mapped (during the code generation stage) over the two physical index registers X and Y available in the M6811 architecture. Thus, the presence of a third physical index register Z in the MPU 6916 architecture can considerably improve the performace of applications compiled with a special GCC 6916 compiler, while requiring a relatively reduced compiler development effort (this would essentially consist of eliminating the nolonger-necessary Z remapping). In line with the key objectives for the architectural upgrade, the introduction of an additional index register would only represent a minor hardware overhead.
A second remark about the GCC compiler is its extensive use of 16-bit arithmetic, especially for pointer manipulation; this led to the introduction of several additional 16-bit instruction, with special emphasis on finding a good compromise between a low hardware overhead and maximum performance gains.

The above remarks led to the following main architectural extesions:

• a new index register Z has been added to the M6811 index registers X and Y, and all instructions that supported the X and Y index registers and/or addressing modes now also support the Z register
• the indexed addressing modes have been complemented with a new singned-offset variation, thus allowing the usage of both legacy 8-bit unsigned and new 8-bit signed offset values for the X, Y, Z index-registers displacement
• a new set of fast index register-update operations has been introduced
• two new 8-bit accumulators H and L have been added to the M6811 accumulators A and B; the new 8-bit accumulators can also be accessed together as a 16-bit accumulator E (similar to accumulator D), and the H, L, and E registers are supported by almost the same instructions that operate on the A, B, and D accumulators
• 16-bit register-to-register arithmetic operations have been included, using the D and E accumulators
• the instructioin set's orthogonality has been improved by introducing several new instructions and featuring some M6811 instructions with missing addressing modes
• all memory-referencing instructions have been featured with a new 16-bit-offset relative addressing mode, thus providing direct hardware support for dynamically-loadable relocatable code and multi-threaded applications
• a simple Floating Point Unit Interface (FPUI) has been incorporated into the processor core, allowing it to be gluelessly extended with any FPUI-compliant FPU

Fig.4 shows the MPU 6916 programming model.

Fig.4: The MPU 6916 programming model

The assembly language orthogonality and compiler-friendly architecture make the MPU 6916 an ideal candidate for new embedded system designs, especially when used in conjunction with the optimized GCC 6916 compiler.
» See the MPU 6916 Software Reference Guide for details