The CDSP-k5 Processor
Technology overview

The CDSP-k5 is the fifth member in the CDSP family of high performance customizable fixed-point DSP cores, featuring high execution speeds for both signal-processing algorithms and standard microprocessor applications. It is meant to be used as an embedded cell in ASICs developed on most of the 0.25u and below technologies. It is highly customizable and can be targeted at a large number of technologies thanks to its parameterized, HDL-only based design.

The CDSP-k5 processes two words in parallel (up to 32 bits each), interpreted as either a complex number, or as a pair of real numbers. The CDSP-k5 hosts a 4-unit complex multiplier allowing speeds of one ComplexMAC/Clock cycle, or two parallel RealMACs/Clock cycle; in both cases saturation logic can be enabled to assist these operations.

The CDSP-k5 includes a high performance, customizable hardware acceleration unit that has been optimized for most of the common DSP algorithms (MAC/FIR/Correlation, LMS, IIR, FFT/iFFT, Search/Min/Max, Matrix/Vector operations). The modular design of the core allows stripped-down versions to be easily obtained, while a number of list-box/check-box customizable features enable on-the-fly tuning of the design to match the user's specifications. The user-guided customization process can thus achieve a highly efficient, low power and small area implementation, making the CDSP-k5 well suited for high-volume, low-cost applications, while also delivering world-class performance.

Some of the CDSP-k5 general registers can be used to interface application-specific hardware accelerators; this offers the user a convenient and effective way to tightly interact with the internal CDSP structure. Also, both the ALU and the MAC can be completely replaced and/or complemented with user-defined hardware structures.

Architectural features:

Customizable features include:

Performance for a typical 0.25u/3V technology implementation: