The CDSP-k2 Processor
Technology overview

The CDSP-k2 is the second member in the CDSP family of high performance customizable fixed-point DSP cores, featuring high execution speeds for both signal-processing algorithms and standard microprocessor applications. It is meant to be used as an embedded cell in ASICs developed on most of the 0.6u and below technologies. It is highly customizable and can be targeted at a large number of technologies thanks to its parameterized, HDL-only based design.

The CDSP-k2 includes an integrated customizable hardware acceleration unit that has been optimized for MAC/FIR/Correlation, FFT/iFFT, and Matrix/Vector operations, thus allowig the processor to be optimized for many common DSP algorithms. The modular design of the core allows stripped-down versions to be easily obtained and enables an easy tuning of the design to match the user's specifications. The user-guided customization process can thus achieve a highly efficient, low power and small area implementation, making the CDSP-k2 well suited for high-volume, low-cost applications, while also delivering world-class performance.


Architectural features:


Customizable features include:


Performance for a typical 0.6u/5V technology implementation: